Links about MMU and Cache in ARM processor

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/93065.aspx

The ARM Subsystem

The AM335X contains ARM Cortex-A8 core, associated memories and peripherals. The Cortex-A8 CPU acts as the overall system controller. The Cortex-A8 can operate in ARM state or Thumb state. The operating modes supported are User Mode(non privileged mode), FIQ mode, IRQ mode, Supervisory mode, Abort mode, System mode, Monitor mode and Undefined mode. The Cortex-A8 ARM subsystem also has MMU, and 32kB L1 Instruction Cache, 32kB L1 Data Cache and 256kB L2 unified cache. CP15 co-processor controls the MMU and Caches.

StarterWare exports APIs for configuring the CPU to operate in privileged mode or non privileged mode and APIs to configure MMU and Cache. The APIs for configuration of the CPU can be found in /include/armv7a/cpu.h and the APIs for configuration of the coprocessor can be found in /include/armv7a/cp15.h

  • Features Not Supported
    • Security extension features
    • Nested interrupts

Programming

Applications can execute in privileged or non-privileged (user) mode of ARM. On entry to the main() function of application, the system will be in privileged mode. However, the application can switch to nonprivileged mode (user mode) using CPUSwitchToUserMode() and back to privileged mode using CPUSwitchToPrivilegedMode() at any point of time. While executing in user mode, the application shall not access system resources which needs privileged access. The privileged mode used in StarterWare is system mode of Cortex-A8 core. Note that all ISRs will be executing in privileged mode.

The Cortex-A8 core CP15 shall be used for cache maintanance operations and enabling/disabling branch prediction. Branch prediction can be enabled using CP15BranchPredictionEnable(). Separate APIs are provided for enabling/disabling instruction and data cache. Also, APIs are given for invalidation and cleaning of caches. Flushing a cache will clear it of any stored data. Cleaning a cache will force it to write the dirty values to main memory. Note that MMU (Memory Management Unit) shall be enabled before enabling the data cache.

  • Creat Page Table. The page table starting address shall be aligned to 16kB by default.
  • Set the translation table base register with the starting address of the page table using Ttb0Set()
  • Enable MMU using MMUEnable()

Cache MMU Example application

Cortex-A8 has supports two levels of caches. Separate L1 instruction and data cache and L2 unified cache. The example application demonstrates the usage of MMU and cache by direct mapping of virtual memory to physical memory. The pages are divided into 1MB sections with only one level of translation. A page can be either cacheable or non-cacheable. The OCMC/DDR memory are marked as cacheable with the following attributes.

  • Section Cacheable Memory Attributes:
    • Non-Secure access.
    • Read/Write access in both user and privileged mode.
    • Executable Code can be present in this section.
    • The section falls into Domain 0.
    • Memory type is Normal Memory
    • Outer Cache Policy is Write Back, Write Allocate
    • Inner Cache Policy is Write Through, No Write Allocate

All other memory are maked non-cacheable, with the following attributes.

  • Section Non-Cacheable Attributes:
    • Non-Secure access.
    • Read/Write access in both user and privileged mode.
    • Executable Code can not be present.

When cache example application is compiled two ELF executable(.out) are generated. They are,

1. uartEdma_Cache.out. This executable demonstrates the effects of not cleaning the cache before a third party (like the EDMA) tries to access the buffer from the main memory.
2. uartEdma_CacheFlush.out. This executable demonstrates the cleaning of the cache before a third party (like the EDMA) tries to access the buffer from the main memory.

  • Execution sequence of uartEdma_Cache.out
  1. Lower case alphabets, a..z, is populated to buffer in the Main Memory (DDR). Note that the cache is not yet enabled
  2. Cache is enabled for entire Main Memory (DDR).
  3. EDMA is programmed to transfer data from buffer to serial console.
  4. Lower case alphabets, a..z, will be printed on the serial console. This is because in step 1, the contents were written to main memory since cache was not enabled
  5. Upper case alphabets, A..Z is populated to buffer. Since buffer is cached, the data populated(A..Z) is updated only to cache and not to Main Memory
  6. EDMA is programmed to transfer data from buffer to serial console.
  7. a..z will be printed on the serial console. This is because EDMA always transfer data from main memory.
  • Execution sequence of uartEdma_CacheFlush.out
  1. Lower case alphabets, a..z, is populated to buffer in the Main Memory (DDR). Note that the cache is not yet enabled
  2. Cache is enabled for entire Main Memory (DDR).
  3. EDMA is programmed to transfer data from buffer to serial console.
  4. Lower case alphabets, a..z, will be printed on the serial console. This is because in step 1, the contents were written to main memory since cache was not enabled
  5. Upper case alphabets, A..Z is populated to buffer. Since buffer is cached, the data populated(A..Z) is updated only to cache and not to Main Memory
  6. Cache is cleaned. When cache is cleaned the data that has got cached(A..Z) is written back to main memory. Now both cache and main memory contains same data.
  7. EDMA is programmed to transfer data from buffer to serial console.
  8. A..Z will be printed on the serial console.