Links about MMU and Cache in ARM processor

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/93065.aspx

The ARM Subsystem

The AM335X contains ARM Cortex-A8 core, associated memories and peripherals. The Cortex-A8 CPU acts as the overall system controller. The Cortex-A8 can operate in ARM state or Thumb state. The operating modes supported are User Mode(non privileged mode), FIQ mode, IRQ mode, Supervisory mode, Abort mode, System mode, Monitor mode and Undefined mode. The Cortex-A8 ARM subsystem also has MMU, and 32kB L1 Instruction Cache, 32kB L1 Data Cache and 256kB L2 unified cache. CP15 co-processor controls the MMU and Caches.

StarterWare exports APIs for configuring the CPU to operate in privileged mode or non privileged mode and APIs to configure MMU and Cache. The APIs for configuration of the CPU can be found in /include/armv7a/cpu.h and the APIs for configuration of the coprocessor can be found in /include/armv7a/cp15.h

  • Features Not Supported
    • Security extension features
    • Nested interrupts

Programming

Applications can execute in privileged or non-privileged (user) mode of ARM. On entry to the main() function of application, the system will be in privileged mode. However, the application can switch to nonprivileged mode (user mode) using CPUSwitchToUserMode() and back to privileged mode using CPUSwitchToPrivilegedMode() at any point of time. While executing in user mode, the application shall not access system resources which needs privileged access. The privileged mode used in StarterWare is system mode of Cortex-A8 core. Note that all ISRs will be executing in privileged mode.

The Cortex-A8 core CP15 shall be used for cache maintanance operations and enabling/disabling branch prediction. Branch prediction can be enabled using CP15BranchPredictionEnable(). Separate APIs are provided for enabling/disabling instruction and data cache. Also, APIs are given for invalidation and cleaning of caches. Flushing a cache will clear it of any stored data. Cleaning a cache will force it to write the dirty values to main memory. Note that MMU (Memory Management Unit) shall be enabled before enabling the data cache.

  • Creat Page Table. The page table starting address shall be aligned to 16kB by default.
  • Set the translation table base register with the starting address of the page table using Ttb0Set()
  • Enable MMU using MMUEnable()

Cache MMU Example application

Cortex-A8 has supports two levels of caches. Separate L1 instruction and data cache and L2 unified cache. The example application demonstrates the usage of MMU and cache by direct mapping of virtual memory to physical memory. The pages are divided into 1MB sections with only one level of translation. A page can be either cacheable or non-cacheable. The OCMC/DDR memory are marked as cacheable with the following attributes.

  • Section Cacheable Memory Attributes:
    • Non-Secure access.
    • Read/Write access in both user and privileged mode.
    • Executable Code can be present in this section.
    • The section falls into Domain 0.
    • Memory type is Normal Memory
    • Outer Cache Policy is Write Back, Write Allocate
    • Inner Cache Policy is Write Through, No Write Allocate

All other memory are maked non-cacheable, with the following attributes.

  • Section Non-Cacheable Attributes:
    • Non-Secure access.
    • Read/Write access in both user and privileged mode.
    • Executable Code can not be present.

When cache example application is compiled two ELF executable(.out) are generated. They are,

1. uartEdma_Cache.out. This executable demonstrates the effects of not cleaning the cache before a third party (like the EDMA) tries to access the buffer from the main memory.
2. uartEdma_CacheFlush.out. This executable demonstrates the cleaning of the cache before a third party (like the EDMA) tries to access the buffer from the main memory.

  • Execution sequence of uartEdma_Cache.out
  1. Lower case alphabets, a..z, is populated to buffer in the Main Memory (DDR). Note that the cache is not yet enabled
  2. Cache is enabled for entire Main Memory (DDR).
  3. EDMA is programmed to transfer data from buffer to serial console.
  4. Lower case alphabets, a..z, will be printed on the serial console. This is because in step 1, the contents were written to main memory since cache was not enabled
  5. Upper case alphabets, A..Z is populated to buffer. Since buffer is cached, the data populated(A..Z) is updated only to cache and not to Main Memory
  6. EDMA is programmed to transfer data from buffer to serial console.
  7. a..z will be printed on the serial console. This is because EDMA always transfer data from main memory.
  • Execution sequence of uartEdma_CacheFlush.out
  1. Lower case alphabets, a..z, is populated to buffer in the Main Memory (DDR). Note that the cache is not yet enabled
  2. Cache is enabled for entire Main Memory (DDR).
  3. EDMA is programmed to transfer data from buffer to serial console.
  4. Lower case alphabets, a..z, will be printed on the serial console. This is because in step 1, the contents were written to main memory since cache was not enabled
  5. Upper case alphabets, A..Z is populated to buffer. Since buffer is cached, the data populated(A..Z) is updated only to cache and not to Main Memory
  6. Cache is cleaned. When cache is cleaned the data that has got cached(A..Z) is written back to main memory. Now both cache and main memory contains same data.
  7. EDMA is programmed to transfer data from buffer to serial console.
  8. A..Z will be printed on the serial console.

BeagleBone DMTimer using Starterware

Some findings regarding Beaglebone DMTimer using Starterware:

There are 8 Timers available from Sitara Processors:

1. Timer 0 : Fixed clock source which is around 32Khz

2. Timer 2-7 : There are 3 possible clock sources

a. The 24-MHz (typ) system clock (CLK_M_OSC) (Starterware use this by default when we call DMTimerXModuleClkConfig)

b. The PER PLL generated 32.768 KHz clock (CLK_32KHZ)

c. The TCLKIN external timer input clock.

3. Timer 1 clock source configuration not available by default from Starterware, probably because its use by DMTimer1 1ms.

4. Timer 5 & 6 clock source configuration not available by default from Starterware, probably because its use by ethernet device.

Turnigy 9x modification service

I'm providing modification service for Turnigy 9x Radio for those who need it. Bellow are the details:

  1. Flash with latest ER9x SGD 50
    I will add programming cable, just the cable without usb programming dongle.
    I will flash it with latest ER9x firmware
  2. Add backlight (I will provide the backlight). Combo with flash mod SGD 15, separate mod SGD 25
  3. Add heptic feedback / vibration motor (I will provide the motor), it will vibrate if there is alarm like Timer, stick center, telemetry alarm. Combo with flash mod SGD 15, separate mod SGD 25
  4. FrSky telemetry modification. I will modify existing TX module so you can pull out the module from the TX, I will provide a cable that you can hook into FrSky module so you can see telemetry data in your TX LCD, activate alarm based on the Telemetry data. Combo with flash mod SGD 60, separate mod SGD 90 (You need to have TX that already flashed with ER9x)
  5. DSM2 mod (Install DSM2 radio module taken from DX4e, DX5, DX6i, HP6DSM, LP4DSM), you need to provide the radio module. This module will allow your Turnigy 9x communicate with all DSM2 compatible RX. Combo with flash mod SGD 30, separate mod SGD 50

For more info, please email yovio@hotmail.com or sms 900 three 6034

Arducopter PID Tuning Guide.

Taken from http://diydrones.com/xn/detail/705844:Comment:792225

Real life conspiring against me, so in brief..

RATE AND STAB TUNING GUIDE PART ONE.

Tuning method one.

1. Set all stab params to ZERO

2. Set all rate params to ZERO

3. Get your gloves and eye protection etc on. Hold copter in hand - go to hover throttle and above

4. Increase rate_P by 0.1 increments, dipping one leg down to 90 degrees and back again. As rate_p increases you will feel increased resistance to your movement.

5. Keep going till the arm you are dipping down starts to bounce (oscillate) as it tries to fight against you. Then back off 0.1 or 0.2. Also try full throttle with copter leant right over (90degrees), this often shows up oscillations that aren't apparent whilst the airframe is horizontal or at less than full beans.

6. Add in rate_d in 0.001 increments. As you hit max level for this you will see the quad sort of twitch, every second or so it will move very slightly and return quickly. When you see this behaviour, don't reduce it yet, but instead add in a bit of rate_I (ensuring you don't go above 50% of your rate_P value) Does this rate_I get rid of the twitches? if so, great try to add a bit more rate_P, again until it starts to oscillate. If it doesn't you will have to back off on rate_D - the level of rate_D seems to depends alot on vibrations. Again tip it right over on full throttle, make sure its all still ok.

NOTE: Possibly a safer first attempt at this would be not to use any rate_I at all, just increase D till you get the twitches and back off a bit then do rate_P.

7. Put in some fairly low values for stab, eg p=3.0, I=0, d=0.001, do another hand test, does it look like it will fly?

8. Set channel 6 to tune stab_P, take off and up stab_p to your liking - (higher values equal better response until you've gone too far then you get the overcompensation oscillations) lower values will give a softer flight, but less locked in.

I've never had any benefit, so far, with stab_I, always ended up at ZERO with this

Stab-d i do last - just small increments (0.001) until there seems to be a detrimental effect on stability

 

Tuning method 2 - i call this the IGOR method :)

Same as above start with all rate and stab params at ZERO, but then firstly add in rate_D till you see the twitches, use rate_I to try and get rid of them if possible (at the level of rate_d that just causes the twitches to start) Then do your rate_P (remembering that rate_I should always be less than 50% of rate_P - Ive seen erratic behaviour if I is too high, you may have to back both I and D off if you find your I value is more than 50% of P).

Then do your stab as described above. If you do both methods you should end up with fairly similar values, if they differ plumb for somewhere in the middle. Always test every setting you arrive at with full throttle, leant right over.

Then fine tune in flight using channel 6 to mess with firstly rate_P and then stab_P.

 

Don't forget the setting i posted are for my small frame, may well be a bit out for yours. I'll try on the 3dr when it arrives. Let me know if this method works for you, if so, I'll be happier releasing part one of the guide, working in isolation here so some confirmation would be nice :)